Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience)

摘要

We present CLEAR (Cross-Layer Exploration for Architecting Resilience), afirst of its kind framework which overcomes a major challenge in the design ofdigital systems that are resilient to reliability failures: achieve desiredresilience targets at minimal costs (energy, power, execution time, area) bycombining resilience techniques across various layers of the system stack(circuit, logic, architecture, software, algorithm). This is also referred toas cross-layer resilience. In this paper, we focus on radiation-induced softerrors in processor cores. We address both single-event upsets (SEUs) andsingle-event multiple upsets (SEMUs) in terrestrial environments. Our frameworkautomatically and systematically explores the large space of comprehensiveresilience techniques and their combinations across various layers of thesystem stack (586 cross-layer combinations in this paper), derivescost-effective solutions that achieve resilience targets at minimal costs, andprovides guidelines for the design of new resilience techniques. Our resultsdemonstrate that a carefully optimized combination of circuit-level hardening,logic-level parity checking, and micro-architectural recovery provides a highlycost-effective soft error resilience solution for general-purpose processorcores. For example, a 50x improvement in silent data corruption rate isachieved at only 2.1% energy cost for an out-of-order core (6.1% for anin-order core) with no speed impact. However, (application-aware) selectivecircuit-level hardening alone, guided by a thorough analysis of the effects ofsoft errors on application benchmarks, provides a cost-effective soft errorresilience solution as well (with ~1% additional energy cost for a 50ximprovement in silent data corruption rate).